学术专著：
[1] 《数字集成电路测试优化——测试压缩、测试功耗优化、测试调度》，北京：科学出版社，2010年6月，ISBN：978-7-03-027894-4（中国科学院科学出版基金资助）
期刊论文：
[1] Jia Li, Qiang Xu, Yu Hu, and Xiaowei Li，“X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing, ” IEEE Transactions on Very Large Scale Integration Systems, 18(7), pp. 1081-1092, 2010.(SCI检索)
[2] Jia Li, Yu Hu, Xiaowei Li, “Scan Chain Design for Shift Power Reduction in Scan-based Testing”, Science China F: Information Sciences, 54(4), April 2011, pp.767-777. (SCI检索)
[3] Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li and Qiang Xu, “Capture-power-aware test data compression using selective encoding”, Integration: The VLSI Journal, 44(3), June 2011, pp. 205-216. (SCI检索)
[4] 李佳，胡瑜，李晓维，王伟。SCANGIN：一种降低扫描测试中动态功耗的方法，《计算机辅助设计与图形学学报》，第18卷，第9期，pages 1391-1396，2006。（EI检索，中文核心）
[5] 李佳，徐勇军，李晓维，王新平。体系结构级功耗分析方法，《系统仿真学报》，第16卷，第12期，pages 2821-2824，2004。（EI检索，中文核心）
国际会议论文：
[1] Jia Li, Qiang Xu and Dong Xiang, “Compression-Aware Capture Power Reduction for At-Speed Testing”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 2011, pp. 806-811.
[2] Jia Li, Yu Huang and Dong Xiang, “Prediction of Compression Bound and Optimization of Compression Architecture for Linear Decompression-based Schemes”, IEEE VLSI Test Symposium (VTS), Dana Point, USA, 2011, pp. 297-302.
[3] Jia Li and Dong Xiang, “DfT Optimization for Pre-Bond Testing of 3D-SICs containing TSVs”, Proc. International Conference on Computer Design (ICCD), Amsterdam, Netherlands, paper 33, 2010.
[4] Jia Li, Xiao Liu, Yubin Chen, Yu Hu, Xiaowei Li, and Qiang Xu. “On Capture Power-Aware Test Data Compression for Scan-Based Testing”, Proc. International Conference of Computer-Aided Design (ICCAD), San Jose, USA, pages 67-72, 2008.
[5] Jia Li, Qiang Xu, Yu Hu and Xiaowei Li. “iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing”, Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Munich, Germany, pages 1184-1189, 2008.
[6] Jia Li, Qiang Xu, Yu Hu and Xiaowei Li. “On Reducing Both Shift and Capture Power for Scan-Based Testing”, Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, pages 653-658, 2008.
[7] Jia LI, Yu HU, and Xiaowei LI. “A Scan Chain Adjustment Technology for Test Power Reduction”, Proc. IEEE 15th Asian Test Symposium (ATS), Fukuoka, Japan, pages11-16, 2006.
[8] Jia LI, Qiang XU, Yu HU, and Xiaowei LI. “On Improving Channel Utilization in Testing NoC-Based Systems”, Dig. of 12th IEEE European Test Symposium (ETS), Freiburg, Germany, 2007.
[9] Jia LI, Qiang Xu, Yu Hu and Xiaowei Li. “Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction”, Proc. IEEE International Symposium on Electronic Design, Test & Applications (DELTA), Hong Kong SAR, pages 26-31, 2008.
[10] Jia LI, Yu HU, and Xiaowei LI. “Test Cost Efficiency Exploration for CMT Processors”, Proc. IEEE TENCON, Taipei, 2007.
[11] Jia LI, Yu HU, Xiaowei LI. “Impact-Factor-Guided X-Filling for Peak Power Reduction during Test”, Proc. IEEE TENCON, Taipei, 2007.
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