1) H. Zhu et al, “Improving yields of high performance 65 nm chips with sputtering top surface of dual stress liner,” VLSI 2007, pp180-181
2) H. Zhu et al, “On the control of short channel effect for MOSFETs with reverse halo implantation” IEEE Electron Device Lett., vol. 28, no. 2, pp168-170, 2007。
3）H. Zhu, “Modeling of impurity diffusion with vacancy-mechanism in diamond lattice and Si1-xGex,” Electrochemical Society Proceedings Volume 2004-07, pp. 923-934
4) H. Zhu et al, “Structure and method to enhance stress in a channel of CMOS devices using a thin gate”, US Patent application number: US20060160317A1
5) H. Zhu et al, “Structure and method for manufacturing planar SOI substrate with multiple orientations”, US7094634.
6) H.S. Yang and H. Zhu, “Method and apparatus for increase strained effect in a transistor channel,” US7118999 and US7462915
7) K. Lee and H. Zhu, “Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom,” US7163867
8) B. Doris et al, “Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers,” US8008724B2
9) H. Zhu and R. S. Averback, "Sintering processes of two nanoparticles: a study by molecular-dynamics simulations," Phil. Mag. Lett. 73, no.1, (1996): 27-33.
10) H. Zhu et al, “Molecular-Dynamics simulations of a 10-keV cascade in beta-NiAl,” Philosophical Magazine A71 735-758, 1995